1. Field of the Invention
The invention relates to a non-volatile memory cell and method of making the same. More particularly, the invention relates to a dual-bit non-volatile memory cell having a local silicon nitride layer, and method of making the same.
2. Description of the Prior Art
Non-volatile memory cells are widely used because they can store data even when no power exists. At present, a non-volatile memory cell can be sub-classified into a floating-gate structure and a silicon-oxide-nitride-oxide-silicon (SONOS) structure. The floating-gate structure uses source-side injection (SSI) or tunneling effect, leading to hot electrons stored in the floating gate. However, the application of the floating-gate structure is increasingly difficult day after day because of the hot electrons punching through along the select gate channel when the source-drain channel length is too short. The SONOS structure uses the SSI effect, leading to hot electrons stored in a silicon nitride layer. Hence, the SONOS structure can be manufactured smaller in size than the floating-gate structure. Therefore, there is a tendency today for the SONOS structure to replace the floating-gate structure.
Please refer to FIG. 1 to FIG. 3, which show the manufacturing method schematics according to the SONOS structure of the prior the art. As shown in FIG. 1, a gate oxide layer 120 on the surface of a substrate 110 is provided. A control gate 130 is formed using a first polysilicon layer (not shown) on the gate oxide layer 120. As shown in FIG. 2, a first oxide silicon layer 141 is formed on the surfaces of the control gate 130, the gate oxide layer 120, and the substrate 110. A silicon nitride layer 142 overlying the first oxide silicon layer 141 is formed next. Then a second oxide silicon layer 143 overlying the silicon nitride layer 142 is formed. Finally, a second polysilicon layer 150 is deposited overlying the second oxide silicon layer 143. As shown in FIG. 3, a self-align etching process is performed to anisotropic etch the second polysilicon layer 150 to form dual split-gates 151, 152 on the second oxide silicon layer 143. The dual split-gates 151, 152 are separated from the control gate 130 by the second oxide silicon layer 143, the silicon nitride layer 142, and the first oxide silicon layer 141.
General speaking, the SONOS structure of the prior art cannot make hot electrons effectively locally inject into and remain stored in the bottom of the silicon nitride layer 142, where the bottom of the silicon nitride layer 142 is defined as the portions of the silicon nitride layer 142 shown in FIG. 3 disposed parallel to the surface of the substrate 110. This is because the bottom of the silicon nitride layer 142 and the portions of the silicon nitride layer 142 near the two vertical sidewalls of the control gate 130 both accept the electrons according to Gaussian distribution when an external electric field is applied. Hence, the hot electrons of the SONOS structure of the prior art are stored dispersedly in the silicon nitride layer 142 set on the surface near the two vertical sidewalls of the control gate 130, reducing the storage ability of the SONOS structure.